figure 1-1: block diagram for the amiga computer family 
 figure 2-1: interlaced bitplane in ram 
 figure 3-1: how the video display picture is produced 
 figure 3-2: what is a pixel? 
 figure 3-3: how bitplanes select a color 
 figure 3-4: significance of bitplane data in selecting colors 
 figure 3-5: interlacing 
 figure 3-6: effect of interlaced mode on edges of objects 
 figure 3-7: memory organization for a basic bitplane 
 figure 3-8: combining bitplanes 
 figure 3-9: positioning the on-screen display 
 figure 3-10: data fetched for the first line when modulo = 0 
 figure 3-11: data fetched for the second line when modulo = 0 
 figure 3-12: a dual-playfield display 
 figure 3-13: how bitplanes are assigned to dual playfields 
 figure 3-14: memory picture larger than the display 
 figure 3-15: data fetch for the first line when modulo = 40 
 figure 3-16: data fetch for the second line when modulo = 40 
 figure 3-17: data layout for first line -- right half of big picture 
 figure 3-18: data layout for second line -- right half of big picture 
 figure 3-19: display window horizontal starting position 
 figure 3-20: display window vertical starting position 
 figure 3-21: display window horizontal stopping position 
 figure 3-22: display window vertical stopping position 
 figure 3-23: vertical scrolling 
 figure 3-24: horizontal scrolling 
 figure 3-25: memory picture larger than the display window 
 figure 3-26: data for line 1 - horizontal scrolling 
 figure 3-27: data for line 2 - horizontal scrolling 
 figure 4-1: defining sprite on-screen position 
 figure 4-2: position of sprites 
 figure 4-3: shape of spaceship 
 figure 4-4: sprite with spaceship shape defined 
 figure 4-5: sprite color definition 
 figure 4-6: color register assignments 
 figure 4-7: data structure layout 
 figure 4-8: sprite priority 
 figure 4-9: typical example of sprite reuse 
 figure 4-10: typical data structure for sprite re-use 
 figure 4-11: overlapping sprites (not attached) 
 figure 4-12: placing sprites next to each other 
 figure 4-13: sprite control circuitry 
 figure 5-1: sine waveform 
 figure 5-2: digitized amplitude values 
 figure 5-3: example sine wave 
 figure 5-4: waveform with multiple cycles 
 figure 5-5: frequency domain plot of low-pass filter 
 figure 5-6: noise-free output (no aliasing distortion) 
 figure 5-7: some aliasing distortion 
 figure 5-8: audio state diagram 
 figure 6-1: how images are stored in memory 
 figure 6-2: bltxptr and bltxmod calculations 
 figure 6-3: blitter minterm venn diagram 
 figure 6-4: extracting a range of columns 
 figure 6-5: use of the fci bit - bit is a 0 
 figure 6-6: use of the fci bit - bit is a 1 
 figure 6-7: single-point vertex example 
 figure 6-8: octants for line drawing 
 figure 6-9: dma time slot allocation 
 figure 6-10: normal 68000 cycle 
 figure 6-11: time slots used by a six bitplane display 
 figure 6-12: time slots used by a high resolution display 
 figure 6-13: blitter block diagram 
 figure 7-1: inter-sprite fixed priorities 
 figure 7-2: analogy for video priority 
 figure 7-3: sprite/playfield priority 
 figure 7-4: interrupt priorities 
 figure 8-1: controller plug and computer connector 
 figure 8-2: mouse quadrature 
 figure 8-3: joystick to counter connections 
 figure 8-4: typical paddle wiring diagram 
 figure 8-5: effects of resistance on charging rate 
 figure 8-6: potentiometer charging circuit 
 figure 8-7: chinon write timing diagram 
 figure 8-8: chinon access timing diagram 
 figure 8-9: chinon read timing diagram 
 figure 8-10: the amiga 1000 keyboard 
 figure 8-11: the amiga 500/2000/3000 keyboard 
 figure 8-12: starting appearance of serdat and shift register 
 figure 8-13: ending appearance of shift register 
 figure d-1: amiga 3000 memory map 
 figure e-1: reading fire buttons 
 figure e-2: pot counters 
 figure e-3: light pen 
 figure k-1: expansion memory map 
 figure k-2: a2000 vs a3000 bus termination 
 figure k-3: expansion bus clocks 
 figure k-4: zorro ii bus arbitration 
 figure k-5: basic zorro iii cycle 
 figure k-6: multiple transfer cycles 
 figure k-7: zorro iii bus arbitration 
 figure k-8: interrupt vector cycle 
 figure k-9: zorro ii within zorro iii 
 figure k-10: read cycle timing 
 figure k-11: write cycle timing 
 figure k-12: multiple transfer cycle timing 
 figure k-13: quick interrupt cycle timing 
 figure k-14: basic zorro iii pic 
 figure k-15: pic with isa option 
 figure k-16: pic with video option 
 figure k-17: configuration register map