TOD consists of a 24-bit binary counter.  Positive edge transitions on
this pin cause the binary counter to increment.  The TOD pin has a passive
pull-up on it.

A programmable alarm is provided for generating an interrupt at a desired
time. The alarm registers are located at the same addresses as the
corresponding TOD registers.  Access to the alarm is governed by a
 control register  bit (crb7).  the alarm is write-only; any read of a tod
address will read time regardless of the state of the ALARM access bit.

A specific sequence of events must be followed for proper setting and
reading of TOD.  TOD is automatically stopped whenever a write to the
register occurs.  The clock will not start again until after a write to
the  lsb event  register.  this assures that tod will always start at the
desired time.

Since a carry from one stage to the next can occur at any time with
respect to a read operation, a latching function is included to keep all
TOD information constant during a read sequence. All TOD registers latch
on a read of  msb event  and remain latched until after a read of
 lsb event . the tod clock continues to count when the output registers
are latched. If only one register is to be read, there is no carry problem
and the register can be read "on the fly" provided that any read of
 msb event  is followed by a read of  lsb event  to disable the latching.

 bit names for write time/alarm or read time