Control bits (CRA5, CRB5-6) allow selection of the clock used to decrement
the timer.  timer a  can count 02 clock pulses or external pulses applied
to the CNT pin.   timer b  can count 02 pulses, external cnt pulses,
 timer a  underflow pulses, or  timer a  underflow pulses while the cnt
pin is held high.

The timer latch is loaded into the timer on any timer underflow, on a
force load, or following a write to the high byte of the pre- scalar while
the timer is stopped.  If the timer is running, a write to the high byte
will load the timer latch but not the counter.