The enhanced Agnus now includes registers for setting a standard
programmable scan rate. The scan rates supported in the V36
graphics.library include:
NTSC (525 lines, 227.5 colorclocks per scan line)
PAL (625 lines, 227.5 colorclocks per scan line)
VGA (525 lines, 114.0 colorclocks per scan line)
The V36 graphics.library controls the variable number of colorclocks on
each horizontal scan line with a combination of registers. Each
combination of registers provides a different frequency of scan rate and
number of lines per display field:
HTOTAL W A Highest number count in horizontal line
Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 10 00
Use 0 0 0 0 0 0 0 0 h8 h7 h6 h5 h4 h3 h2 h1
The value in this register represents the number of 280ns increments on
the horizontal line.
VTOTAL W A Highest numbered vertical line
VTOTAL contains the line number at which to reset the vertical position
counter. This value represents the number of lines in a field(+1). The
exception is if the INTERLACE bit is set (BPLCON0). In this case this
value represents the number of lines in the long field (+2) and the number
of lines in the short field (+1).
Programmable synchronization is implemented through five new enhanced
Agnus registers:
VSSTRT W A Vertical line position for VSYNC start
VSSTOP W A Vertical line position for VSYNC stop
HSSTRT W A Horizontal line position for HSYNC start
HSSTOP W A Horizontal line position for HSYNC stop
HCENTER W A Horizontal position for Vsync on interlace
A reasonable composite can be generated by setting HCENTER half a
horizontal line from HSSTRT, and HBSTOP at (HSSTOP-HSSTRT) before HCENTER,
with HBSTRT at (HSSTOP-HSSTRT) before HSSTRT.
Programmable blanking is implemented through four new ECS Agnus registers:
HBSTRT W A Horizontal line position for HBLANK start
HBSTOP W A Horizontal line position for HBLANK stop
VBSTRT W A Vertical line position for VBLANK start
VBSTOP W A Vertical line position for VBLANK stop